1. The Field of the Invention
The present invention relates to precision etching methods. More particularly, the present invention is directed to a method of precisely etching noble metal films with physical ion etching which is capable of forming high density capacitor electrodes in integrated circuit memory structures.
2. The Relevant Technology
The miniaturization of semiconductor devices has long been a major focus of the integrated circuit manufacturing industry. The semiconductor devices which are being progressively miniaturized include active devices such as transistors and capacitors, as well as resistors, interconnect lines, inter-level contacts, and the many other structures necessary to complete the highly complex integrated circuits currently in demand. This miniaturization has resulted in increasingly compact and efficient integrated circuit chips. It has also been accompanied by an increase in the complexity and number of such semiconductor devices aggregated on a single semiconductor integrated circuit chip.
As the size of various geometric features of semiconductor devices are reduced, new problems arise which must be solved in order to continue to economically and reliably produce integrated circuit chips.
As an example, DRAM memory structures are one type of integrated circuit for which problems must be overcome in order to achieve increased miniaturization and integration levels. One advance which is facilitating the increased miniaturization of memory structures is the use of platinum, a highly conductive and non-reactive material, for the formation of capacitor electrodes. Capacitors are a major component of memory structures such as DRAMs, and are used in many other functions of integrated circuits as well. One type of capacitor which utilizes platinum electrodes is the high dielectric constant capacitor. Ferroelectric capacitors, a specialized form of high dielectric constant capacitor having the capability of reversing polarity, are also being formed with platinum electrodes.
FIG. 1 of the accompanying drawings shows the basic structure of a typical MOS stacked memory structure. As one part of the memory structure, there can be seen a DRAM memory cell, central to which is a high dielectric constant capacitor formed with platinum electrodes. The memory cell includes a silicon substrate 10, above which is formed a pair of active regions 12. A gate region 14 is formed above active regions 12, and an oxide barrier layer 18 having formed on its top surface a word line 16 is located adjacent thereto. Covering these structures is an oxide isolation layer 20, above which is located a lower capacitor electrode 22, which is formed of platinum. Also shown in FIG. 1 is a polysilicon plug 28 which connects lower capacitor electrode 22 and one of the active regions 12. Formed above lower capacitor electrode 22 is a dielectric layer 24. Above dielectric layer 24 is formed an upper capacitor electrode 26 which is also formed of platinum. A planarized passivation layer 30 is located above upper capacitor electrode 26. Extending through passivation layer 30 is a tungsten plug 32. Tungsten plug 32 connects upper capacitor electrode 26 with one of two metal interconnect lines 34. A diffusion barrier layer 36 prevents tungsten plug 32 and upper capacitor electrode 26 from reacting together.
Certain problems are incurred by the use of platinum in forming capacitor electrodes and arise from the need to precisely etch the platinum into the shape of the desired capacitor electrodes. The etching process, which is repeated many times over in the formation of integrated circuit chips, typically comprises at least in part the use of a chemical etchant which reacts with and removes the film or layer being etched. Noble metals such as platinum, however, are not highly reactive with chemical etchants, and consequently require the use of specialized forms of etching. The two methods which are currently used for etching platinum and other noble metals comprise ion beam milling and reactive ion etching (RIE). These processes and other such processes which use ions to physically bombard and thereby etch the film will hereafter collectively be referred to as "physical ion etching."
Ion beam milling comprises a magnetically confined RF or DC plasma which is typically used to generate ions. A semiconductor wafer is physically separated from the plasma in the etch chamber, and a broad ion beam extracted from the plasma is collimated and accelerated to impinge on the wafer surface in a definite direction with respect to the feature to be etched. A magnetic field is often used to force the electrons to follow a helical path between collisions, rather than pass directly from cathode to anode, enhancing the electron path length and ion efficiency at low pressure. A set of grids are also used to extract ions from a source and to direct an ion beam to the wafer surface.
Reactive ion etching typically involves the use of plasma ions in a parallel plate RF reactor to provide a source of energetic particle bombardment of the etched surface. Ion bombardment increases the reaction rate of spontaneously occurring processes and may also prompt reactions which do not occur without radiation. Normally, horizontal surfaces are subjected to both reactive species and impinging ions, while vertical sidewalls are only subjected to reactive species. In the etching of noble metals which are not highly reactive, however, oxygen is typically used as the etchant, and only the physical ion bombardment aspect of reactive ion etching occurs. Consequently, RIE for noble metals is actually a generalized form of ion beam milling.
Physical ion etching processes are advantageous in their ability to etch virtually any material which may be formed on a wafer surface. Nevertheless, certain highly detrimental problems with physical ion etching, and especially when used in the formation of capacitor electrodes, continue to exist. These include the occurrence of redeposition during the etching process. Redeposition involves the tendency of the noble metal to not be volatilized after being etched by the ions, but instead to be redeposited onto the wafer surface and elsewhere in the system. This tendency is illustrated in FIG. 2, which shows a platinum layer 38 being etched by physical ion etching to form a lower capacitor electrode 22.
A patterned photoresist mask 42 is being used to shield the portions of platinum layer 38 which are desired not to be etched, which is lower capacitor electrode 22 seen in FIG. 2. Directional arrows show one direction of emission of the platinum atoms as they are dislodged from platinum layer 38 by the energy of impinging ions from the physical ion etch process. The dislodged platinum atoms come to rest on any surface in their path. One such surface is the sidewall 41 of photoresist mask 42. Consequently, redeposition "ears" or other features are formed on photoresist mask sidewall 41, and remain when photoresist mask 42 is removed, as depicted in FIG. 3. Therein, redeposition ears 40 are shown formed above lower capacitor electrode 22. The size and shape of the redeposition features are determined by the height and slope of the photoresist mask sidewall 41. A shorter sidewall or one with a greater slope will provide less of a surface on which redeposition features can form. Redeposition can cause several rather severe problems, two of which are illustrated in FIGS. 4 and 5.
In FIG. 4, the memory cell has been completed and is shown to be similar to the memory cell of FIG. 1, with the exception of redeposition ears 40 penetrating through dielectric layer 24 and shorting out lower capacitor electrode 22 and upper capacitor electrode 26. While an extreme case is shown for illustration purposes, even shorter ears which do not totally penetrate dielectric layer 24 will increase leakage currents and can cause the capacitor to fail to hold a charge for a sufficient amount of time. The failure to hold a charge is a failure condition which can cause device failure, and can even cause failure of the whole die, the whole wafer, or a batch of wafers where the problem depicted occurs on all wafers to a problematic degree. Consequently, the yield rate of the integrated circuit manufacturing process can be dramatically reduced.
Platinum redeposition during the formation of upper capacitor electrode 26 can also lead to shorts between upper capacitor electrode 26 and metal interconnect lines 34, as shown in FIG. 5. Furthermore, redeposition features can break free from capacitor electrodes 22 and 26 during subsequent processing and be deposited elsewhere on the wafer, often causing shorts between adjacent capacitor electrodes, and also resulting in a failure condition.
An additional problem arising from physical ion etching of noble metals comprises poor critical dimension control of the etching process. In order to produce high density memory structures where capacitors are arrayed side by side with narrow boundaries between them, the tolerances of the separating boundaries between the capacitors must be tightly controlled. The problem with many forms of ion etching is that not only is the noble metal layer etched, but the photoresist material which typically masks the layer is also etched at a substantial rate. This causes the sides of the photoresist mask to shrink, and as a result, the underlying features which were intended to be masked will be etched beyond their intended critical dimensions. A consequence of poor critical dimension control is that the capacitor electrodes being formed will be spaced further apart than desired. This results in decreased device density on the integrated circuit, which in turn reduces the amount of chips that can be formed on a single wafer.
A further problem that arises with physical ion etching is the inability to maintain vertical sidewalls. As the photoresist mask is etched away at the sides, the etchant is given greater and greater access to the sidewalls of the capacitor electrode being etched. This results in rounding or sloping of the capacitor electrode sidewalls. This is undesirable, in that capacitor electrodes with straight sidewalls produce higher capacitance with a lower volume of material. This becomes important in memory structures, where the volume of material in the capacitor electrode is desired to be minimized, both for space savings and because platinum is costly. It is also desired that the capacitor electrode be shorter, as taller electrode heights necessitate more expensive interconnecting structures. Electrodes with vertical sidewalls can be made shorter and will still maintain proper charge rates. Consequently, the inability of physical ion etching to produce vertical sidewalls is also a substantial drawback in the art.
Attempts have been made in the art to overcome the above-recited problems. These include the processes of FIGS. 6 through 8 and of FIGS. 9 through 11. FIG. 6 depicts the initial state of an etch process in which a photoresist mask 44 has been heated and deformed into a rounded shape in an attempt to avoid the occurrence of redeposition. In FIG. 7, where etching is under way, redeposition is seen at the periphery of photoresist mask 44. In FIG. 8, where the etch is completed and photoresist mask 44 has been removed, slight redeposition still occurs, and presents itself in the form of redeposition ears 40. Also, the resulting capacitor electrode will be formed with sloped sidewalls, not the desired vertical sidewalls. A further problem with this method is that it is extremely size sensitive, as it has proven difficult to heat the photoresist masks into the proper rounded shape at smaller sizes.
In FIG. 9, platinum layer 38 is being etched with a prior art process, whereby the sidewalls 45 of photoresist mask 46 are progressively eroded away so that they cannot support redeposition structures. FIG. 10 shows the etch in process, with sloped sidewalls 43 of photoresist mask 46 being continuously removed. Continuous etching of sidewalls 43 of photoresist mask 46 decreases the redeposition problem of platinum layer 38 seen in FIG. 10, but does not totally eliminate it. This is largely due to the fact that it is difficult to coordinate the etch rates of photoresist mask 46 and underlying platinum layer 38 to etch both at the same rate. Furthermore, detrimental side effects result from this method. The resulting capacitor plate 22, shown in FIG. 11, has capacitor electrode sidewalls 45 which are sloped as shown, and are not vertical as is desirable. Critical dimension control is also difficult to maintain under this process, due to the continuous etching of capacitor electrode sidewalls 45.
From the above discussion, it is apparent that a method is needed for etching noble metals, and particularly for physical ion etching of platinum, that avoids the problems of redeposition, poor critical dimension maintenance, and sloping sidewalls. Such a method is further needed with which capacitor electrodes can be formed to have high capacitance, lower tolerances, greater device densities, and less metal volume.